Rapid calibration of bits weights error for high‐resolution successive approximation register ADC
| Autor: | Lu Liu, Shiliu Xu, Xu Daiguo |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Observational error Calibration (statistics) Dynamic range 020208 electrical & electronic engineering 02 engineering and technology Chip 01 natural sciences Hybrid algorithm law.invention Capacitor Integral nonlinearity Control and Systems Engineering law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Shaping Electrical and Electronic Engineering Algorithm Mathematics |
| Zdroj: | IET Circuits, Devices & Systems. 13:368-373 |
| ISSN: | 1751-8598 1751-858X |
| DOI: | 10.1049/iet-cds.2018.5220 |
| Popis: | This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-to-analogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm. |
| Databáze: | OpenAIRE |
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