An 8.5-ns 112-bit transmission gate adder with a conflict-free bypass circuit

Autor:	H. Okada, T. Sato, G. Goto, T. Sukemura, M. Sakate
Rok vydání:	2005
Předmět:	Physics Adder Signal generator Floating point business.industry Carry (arithmetic) Transistor Electrical engineering Propagation delay law.invention Transmission gate CMOS law Hardware_INTEGRATEDCIRCUITS Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_LOGICDESIGN
Zdroj:	1991 Symposium on VLSI Circuits.
DOI:	10.1109/vlsic.1991.760100
Popis:	In this paper, we describe a 112-bit transmission gate adder utilizing a new bypass circuit control scheme to improve performance. The estimated propagation delay time is 8.5 ns and the number of transistors is 6,941, both of which are smaller than those of conventional carry select adders (CSA). The adder is integrated in an area of 0.41 x 3.36 mm/sup 2/ with a density of 5,476 transistors/mm2 achieved by 0. 8-/spl mu/m CMOS technology.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::3de504b16b338baf9849bc051370bbb3 https://doi.org/10.1109/vlsic.1991.760100 Zobrazit plný text záznamu