| Popis: |
Test and measurement equipment often targets high bit-rate PAM4 signals that carry data at rates of several gigabits per second. These PAM4 signals are used to measure the quality of interconnects such as RF cables used in datacenters and deduce several important parameters such as the Bit Error Rate (BER) and the eye diagram, which in turn reveal information about the quality of the medium of transmission. In this paper, we propose the design of a track and hold (T&H) integrated circuit that is able to sample a high-speed incoming PAM4 signal and feed it to an Analog to Digital Converter (ADC). This building block acts as a front-end in optical transceivers carrying sensitive data, where power consumption and cost are a primary concern. The proposed architecture is discussed in detail and a design approach based on the switched capacitor architecture is examined and simulated. The circuit, implemented in a 45 nm CMOS technology, is able to sample an incoming 2 Gbit/s PAM4 signal at 0.2 GS/s, while consuming 42 mW of power and occupying 0.0225 mm2 of area. |
