Pairing-Based Proxy Signature Scheme with Proxy Signer's Privacy Protection
| Autor: | Zeeshan Nadeem Nakhi, Vijay Gopal Sarvepalli, Kaleem Fatima |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Very-large-scale integration
Hardware architecture Virtex Adder business.industry Computer science Reconfigurable computing Filter design Computer architecture VHDL Verilog Hardware design languages Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Computer hardware computer.programming_language |
| Zdroj: | CIS |
| DOI: | 10.1109/cis.2007.49 |
| Popis: | This paper proposes a new approach for the design of hardware architecture for the computation of 2D-DWT for an 8 x 8 image. The key feature of this design is to directly apply 2D-DWT on alternate pixels of an image, called as the Non-Separable method, and implement it on an FPGA. The resulting design was implemented using only 6 adders and 10 multipliers, thus optimizing the number of multipliers and adders required for the computation of 2D-DWT. Thus our approach provides a cost effective solution as compared to the conventional 2D non-separable methods without compromising on speed performance. The design is implemented on Xilinx Virtex II Pro FPGA development kit and synthesized using Xilinx XST (VHDL/Verilog) synthesis tool. Key terms: 2D-DWT, Signal Processing, VLSI, FPGA, filter coefficients, IDWT. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|