A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL

Autor:	Yen Yu Chao, Yuan Cheng Qian, Shen-Iuan Liu
Rok vydání:	2022
Předmět:	Phase-locked loop Loop (topology) Offset (computer science) Computer science Phase noise Electronic engineering Signal edge Electrical and Electronic Engineering Division (mathematics) Sub-sampling Jitter
Zdroj:	IEEE Transactions on Circuits and Systems II: Express Briefs. 69:269-273
ISSN:	1558-3791 1549-7747
Popis:	A sub-sampling phase-locked loop (SSPLL) with a subsampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a 0.18μm CMOS process and its active area is 0.185mm2. At the output frequency of 2.2GHz, the proposed SSPLL achieves an inband phase noise of -111.83dBc/Hz and -116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is -50.3dBc.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::3cef58fb3340942f68300cbdc003f39d https://doi.org/10.1109/tcsii.2021.3105552 Zobrazit plný text záznamu