A 3-GHz dual-modulus prescaler based on improved master-slave DFF
| Autor: | Xuan Jiahui, Xu Jian, Tang Lu, Wang Zhigong |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Frequency synthesizer
Dual-modulus prescaler business.industry Computer science Master/slave Signal edge Frequency divider CMOS Asynchronous communication Embedded system Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Monolithic microwave integrated circuit |
| Zdroj: | 2010 IEEE 12th International Conference on Communication Technology. |
| DOI: | 10.1109/icct.2010.5688989 |
| Popis: | An integrated low-power 3-GHz dual-modulus prescaler (DMP) divided-by-32/33 with a great tolerance to the clock-edge is presented in this paper. A novel structure of CMOS MS-DFF (master-slave D flip-flop) is used in the asynchronous part of the prescaler. The DFF based on the structure can work well in the clocks with longer clock-edge and overcome general-fast-circuit's requirement of clock-edge. The proposed prescaler can work in a quasistatic mode so its power consumption can be reduced. The proposed prescaler is realized with a 0.18-µm CMOS technology. The ratio of the operation range (3.49 GHz) to the maximum operation frequency (3.5 GHz) achieves 99%. |
| Databáze: | OpenAIRE |
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