A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
| Autor: | Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi |
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| Rok vydání: | 2022 |
| Zdroj: | 2022 IEEE International Solid- State Circuits Conference (ISSCC). |
| Databáze: | OpenAIRE |
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