A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing

Autor:	Sai-Weng Sin, Hegong Wei, Mingqiang Guo, Rui P. Martins, Jiaji Mao
Rok vydání:	2019
Předmět:	Very-large-scale integration Analogue electronics CMOS Computer science Hardware_INTEGRATEDCIRCUITS Calibration Skew Electronic engineering Successive approximation ADC Nyquist rate Mixing (physics)
Zdroj:	VLSI Circuits
DOI:	10.23919/vlsic.2019.8778077
Popis:	This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits. We implement the sub-channel SAR with a splitting-combined monotonic switching procedure. The prototype ADC achieves 48.5dB SNDR at Nyquist rate, while the power consumption is 29mW leading to a Walden FOM of 26.7fJ/conv-step.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::3c87546e8350f11a70cabc0d7f0ada5a https://doi.org/10.23919/vlsic.2019.8778077 Zobrazit plný text záznamu