ESD performance enhancement methodologies for CMOS power transistors
| Autor: | Mahadeva Iyer Natarajan, Jian-Hsing Lee |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering business.industry Electrical engineering 020206 networking & telecommunications High voltage Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 01 natural sciences CMOS 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Power semiconductor device High voltage cmos technology Performance enhancement business Hardware_LOGICDESIGN |
| Zdroj: | 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM). |
| DOI: | 10.1109/edtm.2017.7947533 |
| Popis: | Key challenges in providing ESD protection for High Voltage CMOS technology is presented in this paper. Based on that, various methodologies to make the high voltage power transistor ESD self-protecting without changing the device IV characteristics and dimension, for different HV technologies is outlined. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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