| Autor: |
Syed Rubab, James Guthrie, Jing Wang, Clifford Ting, Ruslana Shulyzki, Aynaz Vatankhahghadim, Michael De Vita, Alireza Parsafar, Junhong Zhao, Noam Dolev, Sitaraman V. Iyer, Bahram Zand, Aleksey Tyshchenko, Mike Bichan, Eric Liu, Fulvio Spagna, Shaham Sharifian, Katya Tyshchenko |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
CICC |
| DOI: |
10.1109/cicc48029.2020.9075947 |
| Popis: |
This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating for all analog blocks, continuous data rate support between 1–32 Gb/s, and supporting channel topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10nm process technology. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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