Acceleration of finite field arithmetic algorithms in embedded processing platforms utilizing instruction set extensions

Autor:	Nathan P. Jachimiec, Fernando Martinez-Vallina, Jafar Saniie
Rok vydání:	2007
Předmět:	Standard cell Instruction set Multi-core processor Finite field Datapath Saturation arithmetic Finite field arithmetic Parallel computing Hardware_ARITHMETICANDLOGICSTRUCTURES Elliptic curve cryptography Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Mathematics
Zdroj:	2007 IEEE International Conference on Electro/Information Technology.
DOI:	10.1109/eit.2007.4374484
Popis:	Finite field arithmetic is essential to error correction and cryptography. Instruction set extensions are an alternative to ASICs and DSPs while providing the same performance with embedded CPUs. An instruction set extension is presented that handles various fields in GF(2m). A MIPS DLX processor core is accelerated using an auxiliary processing interface to a finite field arithmetic unit. Additional instructions are added to the DLX core set which are used to create finite field arithmetic benchmarks. The processor core and extensions datapath are synthesized in a standard cell 0.18μm CMOS process achieving a 233MHz clock. The combined DLX and FFU system demonstrates a 355× speed-up when performing elliptical curve projective point doubling in GF(2163).
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::3bf53806f0c71c1b889da91f7a40bf01 https://doi.org/10.1109/eit.2007.4374484 Zobrazit plný text záznamu