A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer
| Autor: | Somnath Kundu, Chris H. Kim, Richard Wong, Shi-Jie Wen, Muqing Liu |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
business.industry
Computer science 020208 electrical & electronic engineering Electrical engineering Regulator Peak current 02 engineering and technology Voltage regulator law.invention Power (physics) Generator (circuit theory) Capacitor CMOS law 0202 electrical engineering electronic engineering information engineering Figure of merit Voltage droop Electrical and Electronic Engineering business Voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:109-120 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm2. A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 $\mu \text{s}$ . It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4–1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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