Autor: |
Su-Mei Chen, Yu-Min Lin, Cheng-Ta Ko, Yu-Wei Huang, Yoshikazu Suzuki, Ren-Shin Cheng, Chang-Chun Lee, Chau-Jie Zhan, Yoshihiro Tsutsumi, Huan-Chun Fu, Chun-Hsien Chien, Yu-Huan Guo, Zhi-Cheng Hsiao, Chia-Wen Fan, Yusuke Sato, Shin-Yi Huang, Junsoo Woo, Chih-Heng Chao, Chien-Ting Liu |
Rok vydání: |
2014 |
Předmět: |
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Zdroj: |
2014 International Conference on Electronics Packaging (ICEP). |
DOI: |
10.1109/icep.2014.6826723 |
Popis: |
A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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