Effectiveness of Si Seed for Selective SiGe Epitaxial Deposition in Recessed Source and Drain for Locally Strained pMOS Application

Autor: Errol Antonio C. Sanchez, S. F. Tzou, Yonah Cho, Yi Cheng Chen, Tony Fu, Chan Lon Yang, Wen S. Hsu, Chin Cheng Chien, Vincent C Chang, Chin I. Liao, Hou Ren Wu, Po Lun Cheng, Jinsong Tang
Rok vydání: 2006
Předmět:
Zdroj: ECS Transactions. 3:245-248
ISSN: 1938-6737
1938-5862
DOI: 10.1149/1.2355817
Popis: A thin layer (15A) of Si seed was employed to help nucleate low temperature selective SiGe epitaxial film in recessed source and drain. In combination with pre-epi wet clean and low temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro-loading effect, and further improved dislocation on the lateral recess interface. Introduction Locally strained Si technology using embedded SiGe has demonstrated improved pMOSFET device performance through hole mobility enhancement [1-3]. Widely used, embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si source and drain in the pMOSFET area. Typical process steps for recessed source and drain SiGe flow is described elsewhere [2]. Prior to selective SiGe epi growth, multiple implants and dry etch of source and drain result in surface damage and chemical residues. Surface quality and cleanliness of the etched Si surfaces have great impact on the morphology and SiGe film quality. Typically, wet clean (in diluted HF) or high temperature bake (> 800 °C) is used as a preepi step to remove surface C and O. Previous study [4] indicated improvement of SiGe film morphology by multiple cycles of wet clean in ozonated DI/SC1/DHF. For most harsh surfaces with severe damage casued by implant and dry etch, use of Si seed layer is employed to nucleate uniform SiGe film with good quality and to minimize micro-loading effect. Experiments and Results Prior to SiGe deposition, device wafers were cleaned in ozonated DI, SC1, and dipped in diluted HF (DHF). Wafers were introduced to the reaction chamber for low temperature bake followed by selective deposition of Si seed and SiGe film in recessed source and drain areas in the pMOS area. Control wafer was process with similar pre-epi wet clean, bake, and deposition without the seed layer. Wafers with severe surface damage did not yield SiGe film growth of good morphology without the seed layer. However, wafers with surface damage resulted in difference in SiGe film morphology with or without the Si seed as shown in Figure 1 and Figure 2. Improved surface morphology is observed as clear faceting and dislocation free around the lateral recess interface in the case with the Si seed. Also, the surface roughness can be healed well in the different density area of wafer by Si seed, further improve micro-loading with the similar incubation time. Micro-loading between isolated area and dense area was improved 92% once Si seed layer was applied. Besides, Si seed implement not only decrease micro-loading effect but also without SiGe quality degradation. Micro-loading was defined as (maximum thickness-minimum thickness)/minimum thickness in the same die. (a) (b) Figure 1. Comparison of morphology of selective grown SiGe film (a) with and (b) without Si seed.
Databáze: OpenAIRE
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