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Video decoders have very demanding processing power and data bandwidth requirements, while power dissipation needs to be very low. This paper describes a new video processor platform, which is the first platform in the market capable of even handling high definition multi standard compliant video codec implementations on a fully programmable MIMD/SIMD processor. It can be configured to deliver the exact processing power needs required for a dedicated implementation, saving chip area size and minimizing power dissipation. It is therefore a suitable solution for all kinds of video codec applications, which differ considerably in their processing power needs. Low power design and minimal development and production costs are crucial for this implementation, asking for an optimized architecture, as presented in this paper. |
