| Popis: |
For the first time, we present a Super Steep Retrograde Well (SSRW) FinFET process utilizing patterned well implants and Si-based epitaxy channels and compare to a state-of-the-art production technology (14LPP) [1]. This flow offers simpler integration and better scalability than current methods using doped glasses [2]. Two low temperature STI options required to minimize dopant diffusion are reported. Compared to POR, long channel SSRW devices show higher transconductance and mobility. Short channel devices, however, show comparable or only incremental improvement in $\mathrm{I}_{\mathrm{EFF}}$ at target $\mathrm{I}_{\mathrm{OFF}}$ and in ring oscillator performance. SRAM yields are high and equivalent to POR, demonstrating no fundamental issues. Keywords: super steep retrograde well, SSRW, CMOS, epitaxy, well implant, FinFET, low temperature STI |
