| Autor: |
Tetsuya Ueda, Kanda Yusuke, Shuji Hirao, Kohei Seo, H. Okamura, K. Tomiyama, Daisuke Inagaki, Kotaro Nomura, Susumu Matsumoto, Kiyomi Hagihara, A. Iwasaki, Naoki Torazawa, T. Shigetoshi, Masayuki Watanabe, S. Suzuki, Toru Hinomura, Hayato Korogi, J. Shibata, T. Hamatani, Makoto Tsutsue, K. Tashiro, Takeshi Harada, Tatsuya Kabe, Muneyuki Matsumoto, Yasunori Morinaga, H. Shimizu, K. Kobayashi, T. Sasaki |
| Rok vydání: |
2010 |
| Předmět: |
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| Zdroj: |
2010 IEEE International Interconnect Technology Conference. |
| DOI: |
10.1109/iitc.2010.5510707 |
| Popis: |
High performance 32nm-node interconnect with ELK (Extremely Low-k, k=3D2.4) has been demonstrated. To suppress process damage and enlarge the via-line space with a wide lithography process margin, robust ELK film with a metal hard mask (MHM) self-aligned via process has been developed. It has accomplished both ultimate low capacitance wirings and high TDDB reliability between Cu lines with vias. In addition, a novel technique of interface engineering between ELK and a liner layer has been developed to strengthen the tolerance against chip packaging. This has achieved highly reliable chip packaging. This complete process has a high manufacturability and it therefore offers a promising technology for the 32-nm node and beyond. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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