A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI
| Autor: | Ramy N. Tadros, Matheus T. Moreira, Ney Calazans, Peter A. Beerel, Weizhe Hua |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering Transistor Detector 02 engineering and technology Energy consumption 020202 computer hardware & architecture law.invention law 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering business Voltage Leakage (electronics) |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 63:858-862 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2016.2536179 |
| Popis: | Resilient design is a promising approach to mitigate the performance losses resulting from process, voltage, and temperature variations and benefits from average-case path activity. Many such design techniques rely on error-detecting latches (EDLs) to identify timing errors. This brief presents a novel low-power low-area EDL that achieves 31.8% less energy consumption, 15.8% less leakage, and 35.4% less area compared with the most efficient previous designs, reducing the overhead and thereby increasing the potential benefits of resilient designs. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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