A 12 MHz data cycle 4 Mb DRAM with pipeline operation

Autor:	Natsuki Kushiyama, T. Oshawa, Yohji Watanabe, Kazuyoshi Muraoka, Tohru Furuyama, Y. Nagahama
Rok vydání:	1991
Předmět:	Very-large-scale integration Engineering Dynamic random-access memory Hardware_MEMORYSTRUCTURES business.industry Pipeline (computing) Chip law.invention Microprocessor CMOS law Electronic engineering Electrical and Electronic Engineering business Computer hardware Dram Random access
Zdroj:	IEEE Journal of Solid-State Circuits. 26:479-483
ISSN:	0018-9200
Popis:	A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 mu m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs. >
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::39dc4559bc4e5706438be680352ae8d6 https://doi.org/10.1109/4.75042 Zobrazit plný text záznamu