An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability

Autor:	Hsie-Chia Chang, Chen-Yi Lee, Yi-Min Lin, Chi-Heng Yang
Rok vydání:	2015
Předmět:	Polynomial code business.industry Computer science Parallel computing Chip CMOS Hardware and Architecture Codec Electrical and Electronic Engineering business Error detection and correction Encoder Software Computer hardware BCH code Shift register
Zdroj:	IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1235-1244
ISSN:	1557-9999 1063-8210
DOI:	10.1109/tvlsi.2014.2338309
Popis:	This paper presents an area-efficient architecture of arbitrary error correction Bose–Chaudhuri–Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting $t = 1$ –24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting $t = 60$ –84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::39b8b9f64d420f00c3a26bf2be0b31cc https://doi.org/10.1109/tvlsi.2014.2338309 Zobrazit plný text záznamu