A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
| Autor: | Ting-Kuei Kuan, Shen-Iuan Liu |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Physics
Open-loop gain 020208 electrical & electronic engineering 020207 software engineering 02 engineering and technology Phase detector Phase-locked loop Noise Control theory Delay-locked loop Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Automatic gain control Electrical and Electronic Engineering Loop gain Jitter |
| Zdroj: | IEEE Journal of Solid-State Circuits. 51:821-831 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2016.2519391 |
| Popis: | This paper presents a digital bang–bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang–bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves $ fs integrated rms jitter and $ dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of $- 245$ dB. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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