A new multilevel inverter with reduced component count and reduced voltage stress
| Autor: | Piyush L. Kamani, Mahmadasraf A. Mulla |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020209 energy 020208 electrical & electronic engineering 02 engineering and technology Network topology Topology law.invention Capacitor Dc voltage law Multilevel inverter 0202 electrical engineering electronic engineering information engineering Electronic engineering business Inverter topology MATLAB computer computer.programming_language Voltage |
| Zdroj: | 2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS). |
| DOI: | 10.1109/sceecs.2016.7509312 |
| Popis: | This paper presents a novel generalized topology of a multilevel inverter. The proposed topology is obtained by extending the developed H-bridge topology. The proposed topology is competent to generate the optimum number of output voltage levels by using minimum number of dc voltage sources. The topology offers reduced value of voltage stress on semiconductor power switches. Utilization of dc voltage source is also improved in proposed topology. The comparison of the proposed topology with conventional topologies confirms the aforesaid improvements. An algorithm is proposed to determine the magnitude of dc voltage source that can generate the optimum number of the output levels. The MATLAB/SIMULINK based simulation results for ninety-three level inverter topology using the proposed algorithm show that all the voltage levels are generated without any discontinuity. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|