A Power-and-Area Efficient $10\times 10$ Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation
| Autor: | Jeongsup Lee, Taehun Yoon, Hyeon-Min Bae, Kwangseok Han, Sangeun Lee, Joon-Yeong Lee, Taeho Kim, Jinho Park |
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| Rok vydání: | 2016 |
| Předmět: |
Engineering
Clock signal business.industry 020208 electrical & electronic engineering Transmitter Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Chip 020202 computer hardware & architecture Voltage-controlled oscillator CMOS Phase noise Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Transceiver business Jitter |
| Zdroj: | IEEE Journal of Solid-State Circuits. 51:2475-2484 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A phase interpolator (PI)-based $10\times 10$ Gb/s bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking the voltage-controlled oscillator (VCO). The VCO clock signal is then redistributed to the PIs, triggering the bootstrapping between the VCO and the PIs. All lanes operate independently as in VCO-based parallel referenceless designs while saving power and area. The measured recovered-data jitter in each lane is $0.93~\textrm {ps}_{rms} $ and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology. The test chip achieves figure-of-merits (mW/Gbps) of 2.03 and 2.13 for the receiver and the transmitter, respectively. |
| Databáze: | OpenAIRE |
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