An Advanced Parallel FPGA Architecture for Bi-Directional Motion Estimation
| Autor: | Ran Liu, Yu Mingyan, Li Zhenzhen, Pengcheng Cao, Huang Yangfan, Min-Jun Deng, Li Donglian, Zhang Yu, Chen Zhuo, Zeng Cailan |
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| Rok vydání: | 2015 |
| Předmět: |
Motion compensation
General Computer Science Pixel business.industry Computer science ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION Frame rate Quarter-pixel motion Motion estimation Verilog Computer vision Artificial intelligence business Field-programmable gate array computer ComputingMethodologies_COMPUTERGRAPHICS computer.programming_language Block-matching algorithm |
| Zdroj: | International Journal of Hybrid Information Technology. 8:235-244 |
| ISSN: | 1738-9968 |
| DOI: | 10.14257/ijhit.2015.8.9.22 |
| Popis: | Motion estimation (ME) and motion compensation (MC) are the key elements for frame rate up-conversion (FRUC) system. Fast and accurate motion estimation is the premise of high quality motion compensation. Unlike conventional unidirectional motion estimation which brings holes, overlaps and blocking artifacts, the bi-directional motion estimation does not produce any overlapped pixel or hole in the interpolated frames. As a result, the bi-directional motion estimation has better performance than conventional unidirectional motion estimation. This paper presents an efficient FPGA architecture targeting bi-directional motion estimation hardware implementation. This proposed architecture can achieve real-time processing for 1280x720@60Hz under 200MHz operating frequency. The design is described in Verilog HDL, verified in Virtex5 FPGA platform. Experimental results show that the proposed architecture has high performance and low cost for bi-directional motion estimation algorithm. This architecture can be used for video post-processing system. |
| Databáze: | OpenAIRE |
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