Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
| Autor: | Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Michitaka Kameyama |
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| Rok vydání: | 2011 |
| Předmět: |
Synchronous circuit
Asynchronous system business.industry Computer science Asynchronous array of simple processors Electronic Optical and Magnetic Materials Proactor pattern Synchronizer Asynchronous communication Electronic engineering Electrical and Electronic Engineering business Computer hardware Hardware_LOGICDESIGN Asynchronous circuit Register-transfer level |
| Zdroj: | IEICE Transactions on Electronics. :1669-1679 |
| ISSN: | 1745-1353 0916-8524 |
| DOI: | 10.1587/transele.e94.c.1669 |
| Popis: | SUMMARY This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than |
| Databáze: | OpenAIRE |
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