Digital signal processing in a 16kbps APC-AB codec by fixed point digital signal processor (FDSP-3)
| Autor: | M. Taka, Shigeyuki Unagami, Tomohiko Taniguchi, Y. Tada, Y. Tomita |
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| Rok vydání: | 2005 |
| Předmět: |
Digital signal processor
Signal processing business.industry Computer science Speech coding Real-time computing Full Rate Adaptive predictive coding Linear predictive coding Multidimensional signal processing Adaptive Multi-Rate audio codec Codec2 Bit rate Codec business Computer hardware Digital signal processing |
| Zdroj: | ICASSP |
| DOI: | 10.1109/icassp.1986.1169050 |
| Popis: | Recently much intensive research of 16kbps Speech coding algorithm has been conducted aiming to reduce the transmission bit rate and yet provides high speech quality. Adaptive predictive coding with adaptive bit allocation (APC-AB)[1] is considered to be one promising approach. However, the processing of this coding algorithm is so complicated that the implementation of the algorithm on a general-purpose signal processor, especially if fixed-point arithmetic DSPs are used, requires careful study of arithmetic operation precision and same way to reduce the number of processing cycles. Taking account of these points, real-time signal processing using a fixed-point signal processing chip (FDSP-3) has been studied, and a prototype codec has been realized. The prototype codec satisfied the CCITT mask of signal-to-total distortion ratio for PCM codecs and showed quality good enough for "toll" speech. |
| Databáze: | OpenAIRE |
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