A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology
| Autor: | E-Hung Chen, Chuen-huei Adam Chou, Makarand Shirasgaonkar, Brian S. Leibowitz, John Eble, Fred Heaton, Barry Daly, Jihong Ren, Bruce Su, Masum Hossain, Jared L. Zerbe, Simon Li, Marko Aleksic, Reza Navid |
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| Rok vydání: | 2015 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 50:814-827 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2014.2374176 |
| Popis: | A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s. |
| Databáze: | OpenAIRE |
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