| Popis: |
In the semiconductor chip manufacturing industry, a method of evaluating characteristics by applying a direct circuit edit at an already manufactured chip level is widely used in order to shorten the product development time and release the product to the market in a short time. [1] This is because, when the fab process is performed by modifying the mask to improve the characteristics as in the conventional method, it takes a lot of time and cost for feedback. Feedback of semiconductor characteristics through circuit edit can save 10-20 times in terms of cost and time. As the process becomes more complex and the pattern size becomes smaller, its benefits become even greater. However, when the chip level circuit edit is applied to the Chip Scale Package (CSP) IC, it is very difficult to apply a general method of the frontside circuit edit, so that the success rate of the circuit edit is lowered. In order to solve this problem, a circuit edit method in the backside direction of the chip has been attempted for many years. [2, 3] However, the backside circuit edit (BCE) has more difficulties than the frontside circuit edit. A typical issue is how to uniformly and precisely control and remove the backside Si of the circuit edit area. The following three points should be considered for this. First, the uniformity of the remaining silicon thickness should be high. Second, it is necessary to control the thickness of remaining silicon to an appropriate thickness in the process of removing backside silicon. Third, it is important not to damage the peripheral circuit during etching and deposition. In this paper, we propose a method to increase the backside circuit edit success rate of CSP IC using Al or Cu metal by controlling these three factors effectively. |
