A 18ns 8KW × 9b NMOS RAM
| Autor: | F. Masuoka, Makoto Segawa, Shoji Ariizumi, T. Kondo, Y. Suzuki, T. Ando, K. Ochii |
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| Rok vydání: | 2005 |
| Předmět: | |
| Zdroj: | 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. |
| DOI: | 10.1109/isscc.1986.1156954 |
| Popis: | An 8K×9 NMOS SRAM using a shared-word line and one-eighth activated row decoder circuit, achieving 18ns access times and 500mW active power dissipation, will be reported. The SRAM was fabricated in 1.5μm double-poly, double-metal process. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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