| Popis: |
The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained Field-Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The said strengths of reconfigurable systems are also beneficial for other application domains, e.g. High-Performance Computing (HPC), since single-core and multicore systems may soon hit scaling limits. |
