| Autor: |
M. J. Lii, C. S. Liu, Hao-Yi Tsai, C. H. Lee, Doug C. H. Yu, Ching-Fang Chen, H. P. Pu |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 IEEE International Interconnect Technology Conference - IITC. |
| Popis: |
The key chip-package-integration (CPI) challenges and solutions in the packaging and assembly of advanced Si technology nodes are reported. The key challenge of CPI due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by optimizing bump structure and materials set including both the organic substrate and solder materials, along with process improvements for both Pb-free solder and Cu bump in flip chip packages. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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