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This paper proposes low-power multiplier architectures based on Vedic mathematics, which is a set of ancient Indian techniques for performing arithmetic operations. The proposed architectures use the Urdhva-Tiryagbhyam sutra from Vedic mathematics, which enables the efficient multiplication of numbers with fewer partial products. The proposed architectures have been implemented and simulated using the 45-nm CMOS technology. The simulation results demonstrate that the proposed architectures achieve significant power savings compared to conventional multipliers while maintaining reasonable area and delay. Therefore, the proposed architectures are suitable for use in low-power and high-performance applications. The Vedic multiplier consists of several sub-modules, each of which performs a specific function in the multiplication process. These submodules include the partial product generator, the multiplier, and the adder. The partial product generator generates partial products based on the input numbers and the Vedic sutras. The multiplier module then combines these partial products to create the final product. Finally, the adder module adds the product to the previous state of the circuit to generate the final result. |
