55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure
| Autor: | Sung Hwan Kim, Jae-Wook Lee, Woo-Seop Kim, Hoon Jeong, Young-Tae Kim, Yong Chul Oh, Nam-Kyun Tak, Yeong-Taek Lee, Han Sung Joo, Ki-Whan Song, Ho Ju Song, Changhyun Kim, Sung In Hong, Kyungseok Oh, Yong Lack Choi |
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| Rok vydání: | 2008 |
| Předmět: |
Materials science
business.industry Transistor Doping Bipolar junction transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor law Logic gate Electric field Hardware_INTEGRATEDCIRCUITS Optoelectronics business Dram Hardware_LOGICDESIGN Static induction transistor |
| Zdroj: | 2008 IEEE International Electron Devices Meeting. |
| Popis: | This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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