Methods for power minimisation in modern VLSI circuits
| Autor: | Milun Jevtić, Bojan Jovanovic |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Very-large-scale integration
General Computer Science Computer science Transistor Real-time computing General Engineering Hardware_PERFORMANCEANDRELIABILITY Chip law.invention CMOS law Dynamic demand Hardware_INTEGRATEDCIRCUITS Electronic engineering Systems design Field-programmable gate array Voltage |
| Zdroj: | International Journal of Reasoning-based Intelligent Systems. 4:46 |
| ISSN: | 1755-0564 1755-0556 |
| DOI: | 10.1504/ijris.2012.046491 |
| Popis: | The continued scaling of the CMOS technology has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. In this paper, we present some widely used techniques for static and dynamic power minimisation in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the design's architectural variations. Along with the overview of power minimisation techniques, as an example, the circuit of binary divider was introduced and implemented in various families FPGAs to demonstrate technological as well as Placement and Routing (PAR) influence on total power consumption. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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