| Popis: |
A novel architecture is proposed for a low-power reconfigurable unsigned multiplier with one level of recursion. Compared with the conventional scheme for n/spl times/n-b unsigned multiplication, which employs four n/2/spl times/n/2 non-additive multiply modules (NMMs), the proposed architecture uses two n/2/spl times/n/2-b NMMs and one (n/2+1)/spl times/(n/2+1) NMM, thereby eliminating one n/2/spl times/n/b-2 NMM. This is done by developing a new principle for NMM-based multiplication, and by developing a novel Wallace tree capable of dealing with partial products of both positive weight and negative weight. The incurred overhead includes two n/2-b carry propagation adders. Simulation results for a 64/spl times/64-b unsigned reconfigurable multiplier in TSMC 0.35-/spl mu/m digital CMOS technology show 20% reduction in transistor count with only 7% increase in multiplication time. |
