Latch-Up Analysis on a 64K Bit Full CMOS Static RAM using a Laser Scanner
| Autor: | M. Noyori, T. Shiragasawa, T. Yonezawa, H. Shimura, K. Kagawa |
|---|---|
| Rok vydání: | 1984 |
| Předmět: |
Magnetoresistive random-access memory
Spectrum analyzer Dynamic random-access memory Computer science Semiconductor memory Hardware_PERFORMANCEANDRELIABILITY law.invention Read-write memory CMOS Hardware_GENERAL law Hardware_INTEGRATEDCIRCUITS Electronic engineering Non-volatile random-access memory Static random-access memory Hardware_ARITHMETICANDLOGICSTRUCTURES Hardware_LOGICDESIGN |
| Zdroj: | 22nd International Reliability Physics Symposium. |
| ISSN: | 0735-0791 |
| Popis: | In order to quantitatively evaluate latch-up sensitivity on scaled CMOS LSIs, an advanced latch-up analyzer with a laser scanner has been developed. As a result of the application of the analyzer to a 64K bit full CMOS static RAM, the analyzer was found to be very useful in latch-up evaluation on CMOS LSIs. Furthermore, high sensitivity regions in the memory cell and a sensitivity distribution in the memory array block, which depend on pattern layout, have been clearly observed on the static RAM. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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