Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking
| Autor: | Winston Shue, Y.J. Lu, W.C. Chiou, C.H. Yu, Y.C. Lin, M. F. Chen, T.D. Wang, C.L. Yu, H.P. Hu, H.J. Tu, M.H. Tseng, K.M. Ching, Ding-Yuan Chen, Hun-Hsien Chang, C.S. Hsu, Ching-Wen Hsiao, W.J. Wu, Kuo-Nan Yang |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Materials science
Wafer-scale integration Through-silicon via business.industry Wafer bonding Electrical engineering Three-dimensional integrated circuit Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention CMOS law Hardware_INTEGRATEDCIRCUITS Optoelectronics Wafer business Leakage (electronics) |
| Zdroj: | 2009 IEEE International Electron Devices Meeting (IEDM). |
| DOI: | 10.1109/iedm.2009.5424350 |
| Popis: | High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and I on -I off characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant changes in Cu/ELK reliability. These excellent characteristics suggest the 300mm 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|