A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor
| Autor: | Naofumi Homma, Ville Yli-Mayry, Yves Mathieu, Makoto Nagata, Kohei Matsuda, Tarik Graba, Jean-Luc Danger, Noriyuki Miura, Shivam Bhasin |
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| Rok vydání: | 2017 |
| Předmět: |
021110 strategic
defence & security studies Computer science business.industry 020208 electrical & electronic engineering Data path 0211 other engineering and technologies Latency (audio) Cryptography 02 engineering and technology Cipher CMOS Logic gate Embedded system 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Energy (signal processing) Hardware_LOGICDESIGN |
| Zdroj: | 2017 Symposium on VLSI Circuits. |
| DOI: | 10.23919/vlsic.2017.8008502 |
| Popis: | An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance. |
| Databáze: | OpenAIRE |
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