Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS
| Autor: | Visvesh S. Sathe, Rajesh Pamula, Fahim ur Rahman |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Physics
020208 electrical & electronic engineering 02 engineering and technology Dissipation Topology Chip law.invention Power (physics) Microprocessor CMOS law 0202 electrical engineering electronic engineering information engineering Range (statistics) Electrical and Electronic Engineering Energy (signal processing) Voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 55:494-504 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2019.2956884 |
| Popis: | This article describes an architecture that auto- nomously sets the operating supply voltage ( $V_{dd}$ ) of a digital system for minimum total energy dissipation, inclusive of regulator loss. The technique directly computes the energy per cycle (EPC) delivered by the supply to the system, to guide $V_{dd}$ adjustment for minimum energy-per-cycle point (MEP; voltage: $V_{MEP}$ and frequency: $f_{MEP}$ ) tracking. The proposed approach avoids significant $V_{dd}$ margins typically required for system operation near-threshold and at sub-threshold $V_{dd}$ levels by employing a unified clock and power ( UniCaP ) architecture that regulates target performance across process, voltage, and temperature (PVT) variation with minimal guardband requirements. Measurement results from a 65-nm CMOS test chip demonstrate the $V_{MEP}$ tracking with less than 5 mV of error within the operating voltage range of 0.38–0.58 V. Measurement results also demonstrate the MEP tracking with temperature variation from −30 °C to 105 °C across varied loading conditions over 20 different test chips. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|