Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Autor:	Zhuo Zhang, Xijiang Lin, Janusz Rajski, Sudhakar M. Reddy, Santiago Remersaro, Irith Pomeranz
Rok vydání:	2006
Předmět:	Engineering Switched-mode power supply business.industry Hardware_PERFORMANCEANDRELIABILITY Automatic test pattern generation Fault (power engineering) Power (physics) Test vector Hardware_INTEGRATEDCIRCUITS Benchmark (computing) Electronic engineering business Electronic circuit Voltage
Zdroj:	ITC
ISSN:	1089-3539
DOI:	10.1109/test.2006.297694
Popis:	When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests. This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests. Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::35d9d7910017af0ba1b0f642c5f69ffb https://doi.org/10.1109/test.2006.297694 Zobrazit plný text záznamu