A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

Autor:	S. Satoh, T. Nakamura, K. Shimizu, K. Takeuchi, H. Iizuka, S. Aritome, R. Shirota
Rok vydání:	2003
Předmět:	Engineering Hardware_MEMORYSTRUCTURES Offset (computer science) Programmable metallization cell business.industry NAND gate law.invention CMOS Hardware_GENERAL law Low-power electronics Charge trap flash Electronic engineering business Low voltage EEPROM
Zdroj:	International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
DOI:	10.1109/iedm.1999.823895
Popis:	This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduced for the first time. The program disturbance is decreased by two decades of magnitude in 0.1 /spl mu/m generation, without area penalty and additional process steps. Furthermore, the program disturbance is not increased by scaling and low voltage operation. Therefore, GOC-NAND is indispensable technology for gigabit-scaled NAND EEPROMs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::35b81b16615fcc006aa9bd87df49f3c8 https://doi.org/10.1109/iedm.1999.823895 Zobrazit plný text záznamu