26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection
| Autor: | Pawel Owczarczyk, Michael A. Sperling, Pierce Chuang, Phillip J. Restle, Joshua Friedrich, Christos Vezyrtzis, Timothy Diemoz, Paul H. Muench, Eric Fluhr, Michael Stephen Floyd |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering business.industry 020208 electrical & electronic engineering Transistor Clock rate Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 01 natural sciences law.invention Power (physics) Threshold voltage law 0103 physical sciences Timing margin DPLL algorithm Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Voltage droop business Jitter |
| Zdroj: | ISSCC |
| Popis: | Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (V DD ) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked loop (DPLL) to immediately reduce clock frequency in response. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|