| Autor: |
Daesik Moon, Jung-Hwan Choi, Seok-Hun Hyun, Jung-Bae Lee, Sung-Woo Yoon, Su-Jin Park, Dong-Hoon Lee, Jin-Hyeok Baek, Seung-Jun Bae, Y.S. Park, Hui-Kap Yang, Ki-Han Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Chang-Kyo Lee, Bok-Gue Park, Young-Jae Kim, Jin-Seok Heo, Kyungryun Kim, Soobong Jang, Ki-Ho Kim, Joung-Wook Moon, Kwang-Il Park, Jae-Hyung Lee |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
VLSI Circuits |
| DOI: |
10.23919/vlsic.2019.8778102 |
| Popis: |
A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. Providing a reconfigurable LVSTL with a mode detection scheme to support two different DRAM interface standards (LPDDR4/4X) depending on I/O supply voltage $(V_{DDQ})$, a proposed design can maintain the system compatibility and longevity to the legacy controller and the PHY structure. The VHK for LPDDR4 enables the 3.2Gb/s operation in the un-terminated load similar to LPDDR4X by alleviating the inter symbol interference (ISI) through the controlled leakage current. In a ZQ calibration, the proposed ZQ algorithm achieves fast ZQ code searching, the calibration time can be reduced by 30% in PVT variation. Moreover, an internal ZQ calibration (IZQC) is newly adopted to minimize the variation of the driver strength to PVT variation. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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