Reducing Transistor Variability for High Performance Low Power Chips
| Autor: | Lawrence T. Clark, Robert Rogenmoser |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Very-large-scale integration
business.industry Computer science Transistor Drain-induced barrier lowering Hardware_PERFORMANCEANDRELIABILITY Threshold voltage law.invention Integrated injection logic CMOS Hardware_GENERAL Hardware and Architecture law Embedded system Hardware_INTEGRATEDCIRCUITS Electronic engineering Field-effect transistor Electrical and Electronic Engineering business Software Hardware_LOGICDESIGN Voltage |
| Zdroj: | IEEE Micro. 33:18-26 |
| ISSN: | 0272-1732 |
| DOI: | 10.1109/mm.2013.10 |
| Popis: | CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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