0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme

Autor:	Hiroyuki Yamauchi, Y. Yamagami, Akinori Shibayama, Ichiro Hatanaka, Toshikazu Suzuki, Hironori Akamatsu
Rok vydání:	2005
Předmět:	Scheme (programming language) business.industry Computer science Electronic engineering Access control Cosmic ray Static random-access memory business Cmos process computer computer.programming_language
Zdroj:	ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
Popis:	A device-fluctuation-tolerant access-control scheme and a unique cosmic-ray-immune hidden-ECC scheme are implemented in a 32kB SRAM in a 0.13 /spl mu/m CMOS process. The SRAM operates at 0.3V at 6.8MHz under severe device fluctuations. Operation ranges from 30MHz at 0.4V to 960MHz at 1.5V. The hidden-ECC reduces access-timing and the calculated soft-error-rate is reduced by 3.6/spl times/10/sup 10/ per MB.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::34e4288007a866592f5dc3ac070a312c https://doi.org/10.1109/isscc.2005.1494080 Zobrazit plný text záznamu