| Autor: |
Pusit Suriyavejwongs, Boonchuay Supmonchai, Karn Opasjumruskit |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). |
| DOI: |
10.1109/edssc.2015.7285081 |
| Popis: |
The capacitor-less LDO regulator with slew-rate enhancement disabling scheme has been introduced and postlayout simulated in 2P4M 0.35-μm CMOS process. The output voltage can be adjusted on-the-fly from 0.9 to 1.6 V with minimum supply voltage of 1.6 V (0.1 V dropout). The regulator consumes less than 78 μA quiescent current and can supply 0– 100 mA load with 5 μs settling time. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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