BIST-aided scan test - a new method for test cost reduction

Autor:	Takahisa Hiraide, Kwame Osei Boateng, K. Itaya, Hideaki Konishi, T. Mochiyama, M. Emori, H. Yamanaka
Rok vydání:	2003
Předmět:	Engineering business.industry Scan chain Test compression Hardware_PERFORMANCEANDRELIABILITY Automatic test pattern generation Test (assessment) Reliability engineering Cost reduction Built-in self-test Fault coverage Hardware_INTEGRATEDCIRCUITS business Hardware_LOGICDESIGN Electronic circuit
Zdroj:	VTS
DOI:	10.1109/vtest.2003.1197675
Popis:	It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::3434030ba1d459152a54baab418d9266 https://doi.org/10.1109/vtest.2003.1197675 Zobrazit plný text záznamu