RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience
| Autor: | Veit B. Kleeberger, Wolfgang Rosenstiel, Peter Marwedel, Sani R. Nassif, Johannes Maximilian Kühn, Semeen Rehman, Michael Glaß, Andreas Herkersdorf, Ulf Schlichtmann, Muhammad Shafique, Daniel Mueller-Gritschneder, Jorg Henkel, Norbert Wehn, Michael Engel, Jürgen Teich, Christian Weis |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Finite-state machine Computer science Noise (signal processing) Probabilistic logic 02 engineering and technology MPSoC 01 natural sciences 020202 computer hardware & architecture Signal transition Computer engineering 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Bit error rate System on a chip Abstraction (linguistics) |
| Zdroj: | Dependable Embedded Systems ISBN: 9783030520168 |
| DOI: | 10.1007/978-3-030-52017-5_1 |
| Popis: | The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario. |
| Databáze: | OpenAIRE |
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