| Autor: |
T. Shano, K. Kanebako, M. Kosakai, Y. Komatsu, S. Yoshikawa, Masaki Fujiu, Michio Nakagawa, A. Inoue, K. Iwasa, T. Takahashi, H. Tabata, Katsuaki Isobe, S. Hoshi, Hiroto Nakai, K. Kanazawa, Noboru Shibata, N. Motohashi, T. Shimizu, Mitsuaki Honma, Kenichi Imamiya, Hiroshi Maejima, K. Nagaba, T. Kawaai |
| Rok vydání: |
2007 |
| Předmět: |
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| Zdroj: |
2007 IEEE Symposium on VLSI Circuits. |
| Popis: |
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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