| Autor: |
Said Belkouch, Mohamed Najoui, Assia Arsalane, Abdessamad Klilou |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
2020 International Symposium on Advanced Electrical and Communication Technologies (ISAECT). |
| DOI: |
10.1109/isaect50560.2020.9523653 |
| Popis: |
Digital Pulse-Doppler radar signal processing chain (DPDR-SPC) is a computationally intensive chain. A massively parallel-embedded computing system was presented in this paper in order to meet real-time constraints. This system is based on sixteen digital signal processor (DSP) cores interconnected using Serial RapidIO (SRIO) protocol. A parallel-pipelined mapping model was proposed in this paper. In fact, this model has been optimized based on an efficient scheduling and mapping of the whole DPDR-SPC and an optimized SRIO communications approaches. In order to do that, the inter-processor communication time has been overlapped with computing time and data arrangements were performed using direct memory access (DMA). A use case of the DPDR-SPC has been experienced to prove the concept of the proposed mapping model. Experimental result shows a parallel efficiency of 80%. Compared to previous work, the proposed mapping technique is efficient and more scalable. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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